1. Technical Field
The present invention relates to a method and apparatus for data processing in general, and in particular to a method and apparatus for rounding intermediate normalized mantissas. Still more particularly, the present invention relates to a method and apparatus for rounding intermediate normalized mantissas within a floating-point processor.
2. Description of the Prior Art
According to the IEEE 754 standard, floating-point numbers are represented by three elements, namely, a binary sign bit, a binary encoded exponent, and a binary encoded mantissa. In the case of a normalized floating-point number, the exponent is that which ensures the first digit of the mantissa is a logical one, except for special cases such as zero, infinities, and unrepresentable numbers.
Typically, within a floating-point processor, an intermediate normalized mantissa of a floating-point number must be rounded. The rounding process generally involves an increment operation followed by a selection for each bit of the output from a bit from an unincremented mantissa, a bit from an incremented mantissa, or a constant value. The constant value can either be a constant that is dictated by a special case (such as a zero result, an overflow, an underflow, or an invalid operation) or by the casting of the result to a lower precision (such as rounding the result to a single precision). The present disclosure provides an improved method and apparatus for rounding intermediate normalized mantissas within a floating-point processor.
In accordance with a preferred embodiment of the present invention, an apparatus for rounding intermediate normalized mantissas within a floating-point processor includes an AND circuit, a selection circuit, and a multiplexor. The AND circuit generates an AND signal and its complement from a normalized mantissa. The selection circuit generates a select_AND signal and its complement from the normalized mantissa. The multiplexor, which is coupled to the AND circuit and the selection circuit, chooses either the AND signal or its complement signal as a rounded normalized mantissa according to the select_AND signal and its complement signal from the selection circuit.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.